Gate Level Modeling
If a circuit is represented completely using basic gates it is called gate level modeling. For example refer the below circuit of half adder where we can represent it simply using the AND and XOR gates. this level of abstraction involves describing the circuit using primitive logic gates such as AND, OR, XOR, etc. This level provides a detailed representation of the circuit’s structure and logic. Given Below is the RTL Code for Half Adder.
module half_adder(input a,b, output sum,carry); xor x1(sum, a, b); and a1(carry, a, b); endmodule
Getting Started with Verilog
For a long time, computer programming languages like FORTRAN, Pascal, and C were used to describe computer programs and their code execution is sequential. But there isn’t any language to describe the digital circuits. This is when Hardware Description Language(HDL) came into play. HDLs are even popular for verification purposes. There are mainly two types of HDL:
- Verilog HDL
- VHDL (Very High-Speed was Integrated Circuit (VHSIC) Hardware Description Language)
Note: Verilog HDL and VHDL aren’t the same. VHDL was used before Verilog came into existence. the difference between them will be discussed in the later part.
Table of Content
- What is Verilog?
- Gate Level Modeling
- Data-Flow Modeling
- Behavioral Modeling
- Operators
- Identifiers and Keywords
- Datatypes
- Module Declaration
- Classification of Verilog
- Verilog HDL Vs VHDL
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