Behavioral Modeling
This is the highest level of abstraction in Verilog. At this level the designers describe the functionality of the circuit without specifying the functionality and structure of digital circuit. This modeling will be helpful because it focuses on what the circuit should do rather than how it should be implemented.
module half_adder(input a,b, output reg sum,carry);
always@(*)
begin
sum = a ^ b;
carry = a & b;
endendmodule
Getting Started with Verilog
For a long time, computer programming languages like FORTRAN, Pascal, and C were used to describe computer programs and their code execution is sequential. But there isn’t any language to describe the digital circuits. This is when Hardware Description Language(HDL) came into play. HDLs are even popular for verification purposes. There are mainly two types of HDL:
- Verilog HDL
- VHDL (Very High-Speed was Integrated Circuit (VHSIC) Hardware Description Language)
Note: Verilog HDL and VHDL aren’t the same. VHDL was used before Verilog came into existence. the difference between them will be discussed in the later part.
Table of Content
- What is Verilog?
- Gate Level Modeling
- Data-Flow Modeling
- Behavioral Modeling
- Operators
- Identifiers and Keywords
- Datatypes
- Module Declaration
- Classification of Verilog
- Verilog HDL Vs VHDL
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