Error Generation
Error is introduced as follows :
- Generate a random number, say r1. Perform r1 % 2. If you get a 0 do not introduce error and send original bits. If you get a 1, introduce error.
- To decide which bit will be in error, generate another random number, say r2. Perform r2 %(size of received frame). Assume you get a value i as the outcome. Flip the i-th bit. Now send it to the receiver.
Save this file as error_gen.py.
Python3
import random class err_gen() : def induce_err( self , in_str) : chk = ( int )(random.random() * 1000 ) % 2 if not chk : return in_str idx = ( int )(random.random() * 1000 ) % len (in_str) f_bit = '*' if in_str[idx] = = '0' : f_bit = '1' else : f_bit = '0' out_str = in_str[ : idx] + f_bit + in_str[idx + 1 : ] return out_str if __name__ = = "__main__" : data = "1001010" print ( "Initial : " , data) print ( "Final : " , err_gen().induce_err(data)) |
Output:
Initial : 1001010 Final : 0001010
Python – Stop & Wait Implementation using CRC
Stop and wait protocol is an error control protocol, in this protocol the sender sends data packets one at a time and waits for positive acknowledgment from the receiver’s side, if acknowledgment is received then the sender sends the next data packet else it’ll resend the previous packet until a positive acknowledgment is not received.
Note: To get more info on what is stop and wait protocol, refer Stop and Wait ARQ article.
CRC aka Cyclic redundancy check is an error detection mechanism, its procedure is as follows.
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